Tutorial
Date: 13/11/2024 - 14/11/2024
Location: Prague, Czech Republic
Technical Chair:
Dr. Reinhold Bayerer, Physics of Power Electronics (DE)
Prof. Thomas Basler, Chemnitz University of Technology (DE)
ECPE Contact:
Marietta Di Dio
+49 911 81 02 88 – 13
marietta.didio@ecpe.org
Registration Deadline: 6 November 2024
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This tutorial will explore the various effects of parasitic inductance (LS) in power electronics. As power and current densities continue to grow, parasitic inductance and resistance are becoming increasingly significant limiting factors. The use of unipolar devices, such as WBG (wide-bandgap) devices, requires minimizing parasitic inductance to enable fast switching. The figure of merit is the product of parasitic inductance times rated current (LS * Inom), which increases with current density if designs do not improve.
The issue is not only overvoltage during turn-off; for bipolar power semiconductors like IGBTs and freewheeling diodes, parasitic inductance can lead to unfavourable current waveforms. In systems with snubber capacitors in addition to the DC-link capacitor, and parasitic inductance between them, oscillations between these capacitors can occur.
When considering parallel power semiconductors, the presence of even very small parasitic inductance can affect current sharing in voltage-controlled devices like IGBTs, MOSFETs, and JFETs. Parasitic inductance within the control circuit (gate circuit) can decouple the driver and gates of these devices, leading to issues such as increased short-circuit current.
The tutorial will begin with an introduction to the basics of switching inductive loads and a discussion of the related waveforms. This will be followed by an investigation into the different effects of parasitic inductance, along with an exploration of the relevant power semiconductor physics. The discussion on paralleling will be accompanied by case studies. Another key focus will be the design of conductor geometries and systems for low parasitic inductance and good current sharing. The conclusion will summarize the benefits of such system designs, including clean switching and reduced losses.
Participants are encouraged to contribute to the tutorial by sharing their own examples or challenges in power circuits. Circuit designs or waveforms from power circuits provided by participants will be discussed. If participants can supply such examples, an online meeting will be arranged two weeks after the tutorial, on November 27. Further details will be provided during the tutorial.
All presentations and discussions will be in English language.
Tutorial
Date: 13/11/2024 - 14/11/2024
Location: Prague, Czech Republic
Technical Chair:
Dr. Reinhold Bayerer, Physics of Power Electronics (DE)
Prof. Thomas Basler, Chemnitz University of Technology (DE)
ECPE Contact:
Marietta Di Dio
+49 911 81 02 88 – 13
marietta.didio@ecpe.org
Registration Deadline: 6 November 2024
Postal address ECPE e.V.:
ECPE European Center for Power Electronics e.V.
Ostendstrasse 181
D-90482 Nuremberg, Germany
Phone: +49 (0)911 81 02 88-0
© 2018 ECPE European Center for Power Electronics e.V.